At-speed testing is an important method for testing internal integrated synchronous circuit functionality, and is essential in enabling reliable and cost-effective testing of semiconductor devices to be performed. However, at-speed testing power consumption is higher than functional mode power consumption. During the capture period, a circuit can draw a large supply current and cause a large voltage drop (“IR-drop”) over the power and ground distribution network (PDN). Excessive IR-drops in the PDN can reduce switching speeds and noise margins of circuits, and inject noise which might lead to functional failures. Significantly, the higher-than-functional switching activity created during at-speed testing can result in such excessive IR-drops, which can cause functionally correct devices to fail the at-speed testing, which can lead to an unnecessarily low product yield.
The effort of power consumption reduction during at-speed testing to avoid excessive IR-drops occurs at the design stage, using ATPG (Automatic Test Pattern Generation) tools. Conventional ATPG tools use toggling based metrics such as Weighted Switching Activity (WSA) values for identifying test patterns that could cause large IR-drops, so that those test patterns can be filtered out. The WSA of a circuit caused by a particular test pattern is typically calculated by identifying all gates in the circuit that are caused to switch state by the test pattern, determining a weighted value for each switching gate based on, for example, the fan-out count for the respective gate, and summing the weighted gate values of the switching gates to obtain the weighting switching activity (WSA) value for the circuit caused by the particular test pattern.
However, toggling based metrics, such as WSA values, have been found to have only a limited correlation with IR-drops; sometimes a circuit with a higher toggle value does not suffer from a high IR-drop, whilst a circuit with a lower toggle value might suffer a high from IR-drop. As a result, ATPG tools that rely on toggle metrics to identify test patterns that could cause large IR-drops tend to be over constrained, causing the need for more test patterns (and thus more test time), while providing less coverage.
Reliable IR-drop-aware test pattern generation is required to avoid yield loss, increase test coverage and decrease test time. Test time has serious impact on the product cost (scan tests cost is 20% to 50% of the total test cost, while the test cost is 50% of the product cost). Setting appropriate constraints on the ATPG tool may save 10%-30% (or more) of the total patterns' duration. So the potential for saving is 3%-5% of the product cost.